This invention relates to a method of producing a VDMOS (vertical double diffused metal-on-semiconductor) device particularly a power VDMOS device.
Power VDMOS devices are well known in the art. Thus such devices and method of their fabrication are described in Goodman et al. U.S. Pat. No. 4,587,713, Contiero et al. U.S. Pat. No. 4,774,198, Suzuki European Patent Application 0336393, Nakaqawa et al. U.S. Pat. No. 4,680,604 and other references described on pages 8 and 9 of application Ser. No. 07/842853 filed on Feb. 25, 1992 by the Applicant Manjin J. Kim and now U.S. Pat. No. 5,268,586 and the contents of which are hereby incorporated by reference.
Such devices are used, for example, as high current power switches and as rectifiers for high frequency power supplies.
For many purposes including reasons of economy it is useful that the density of the VDMOS devices provided on a semiconductor substrate be as high as possible.
A problem with increasing the density of the VDMOS devices as made according to these known methods is that the trench contact between the X doped source at the y doped body (where x is p or n and y is a dopant opposite to that of x) requires a large area. As a result the density of a VDMOS device that can be provided for a given semiconductor substrate area is severely limited.
This is true also for the device produced by method disclosed in the above-noted Applicants' U.S. Pat. No. 5,268,586.